The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device, which has a bias circuit and is supplied by a plurality of power sources, for prohibiting production of latch-up for any power inputting sequence.
Recently, since a CPU is developed to be operated by a low-voltage power source and so on, there is a case in which one semiconductor device has a plurality of power supply terminals and is supplied by different power sources. For example, such a semiconductor device has, besides a power source for the inside of a chip, a power source of a different voltage for an interface, an output buffer, etc., and is operated by these plurality of power sources.
FIG. 6 shows a sectional view of a CMOS static RAM operated by a plurality of voltages (cf. Unexamined Japanese Patent Application Pub. No. 06-243687). This RAM comprises a memory array and X and Y address registers. This structure is achieved by a Silicon On Insulation (SOI) semiconductor substrate in which P-type and N-type semiconductor substrates are combined and an insulator is located in the combined substrate. By adopting an SOI, high speed performance is easily achieved because of a low parasitic capacity of lines. In addition, latch-up is prevented because an NMOS transistor and a PMOS transistor are formed in a stripe state. "Latch-up" means a situation where a current continuously flows from a power source terminal to an earth terminal by existence of a parasitic transistor in a CMOS transistor structure.
In FIG. 6, a memory array MA and a X address register XD are formed. In the memory array MA, a PMOS transistor 69 is formed on a substrate region, i.e., an N-type well 67 separated by insulators 63 and 64. In addition, an NMOS transistor 68 is formed on a P.sup.- -type well 66 separated by insulators 62 and 63. Furthermore, an N.sup.+ region is formed on the N.sup.- -type well 67, and earth potential Vss is supplied to it as a substrate bias voltage. In addition, a P.sup.+ region is formed on the P.sup.- -type well 66, and a power source voltage VDD2 is supplied to it as a substrate bias voltage.
On the other hand, in the X address recorder XD, an NMOS transistor 71 is formed on a P.sup.- -type well 70 separated by insulators 61 and 62. Furthermore, a P.sup.+ region is formed on the P.sup.- -type well 70, and a power source voltage VDD1, which is different from a power source voltage VDD2, is supplied to it as a substrate bias voltage.
As described above, in a semiconductor device which has a plurality of parts operated by different power voltages, by supplying the power voltages and a earth potential as substrate bias voltages, it is possible to prevent a threshold voltage of MOS transistors from increasing to an unnecessarily high level and to achieve high-speed operation of a semiconductor device such as a RAM.
The occurrence of the latch-up can be prevented in an SOI, however, in a semiconductor device which does not have an insulator, the latch-up may be generated.